The present invention generally relates to an electron beam exposure data processing method suitable for writing a pattern on a substrate such as a wafer, an electron beam resist or a reticle. The present invention is further concerned with an electron means exposure method and apparatus using the electron beam exposure data processing method.
As is well known, an electron beam exposure process is very effective to write a fine (submicron) pattern on a substrate. In electron beam lithography, the proximity effect occurs, which results from the fact that electrons are forward scattered and backscattered when they hit the substrate. The forward scattered or backscattered electrons expose the substrate so that an exposed pattern having dimensions greater than designed dimensions thereof is formed. In some cases, the forward scattered and/or backscattered electrons affect the exposure of an adjacent pattern. For the above-mentioned reasons, there is a need for correcting the proximity effect.
A conventional method of correcting the proximity effect in electron beam lithography includes steps of calculating the distance between a pattern of concern and each adjacent pattern and adjusting the exposure dose on the basis of the calculated distance (see M. Parikh, "SELF-CONSISTENT PROXIMITY EFFECT CORRECTION TECHNIQUE FOR RESIST EXPOSURE (SPECTRE)", J. Appl. Phys. 15(3), May/June 1978, pp. 931-934; M. Suzuki, "PROXIMITY EFFECT CORRECTING METHOD IN ELECTRON BEAM EXPOSURE", Jap. Appl. Phys., 29p-S-6, 1979; N. Sugiyama, "PROXIMITY CORRECTING METHOD IN ELECTRON-BEAM LITHOGRAPHY", Jap. Appl. Phys., 4a-E-3, 1979; Japanese Laid-Open Patent Application No. 56-48136 (1981); or Japanese Laid-Open Patent Application No. 56-48136 filed on May 1, 1981).
There is also known a different approach to proximity effect corrections (dimension corrections), which writes a pattern which is scaled down by a factor equal to an extended area due to the scattered electrons (see M. Parikh, "CORRECTIONS TO PROXIMITY EFFECTS IN ELECTRON BEAM LITHOGRAPHY", J. Appl. Phys. 50(6), June, 1979, pp. 4371-4377; or H. Sewell, J. Vac. Sci. Technol. 15(3), May/June 1978, pp. 927-930). Further, there is known a method of correcting both the dimensions and exposure dose (see, Y. Machida, "STUDY OF CORRECTING INTRAPATTERN PROXIMITY EFFECT TO NEGATIVE RESIST", Jap. Appl. Phys., 3p-A-10, 1982).
The conventional methods proposed in the above-mentioned papers precisely write patterns. However, it takes an extremely long time to refer to patterns adjacent to a pattern of interest and calculate adjusted dimensions of the pattern and/or an adjusted exposure dose for the pattern of interest.
Recently, various framing processes directed to proximity effect correction have been proposed (see E. Kratschmer, "VERIFICATION OF A PROXIMITY EFFECT CORRECTION PROGRAM IN ELECTRON-BEAM LITHOGRAPHY", J. Vac. Sci. Technol., 19(4), Nov./Dec. 1981, pp. 1264-1268; W. W al., "A MODEL FOR OPTIMIZING CPU TIME FOR PROXIMITY CORRECTION", J. Vac. Sci. Technol., 19(4), Nov./Dec. 1981, pp. 1300-1303; K. Kobayashi, "PROXIMITY EFFECT CORRECTING METHOD (III) IN ELECTRON-BEAM LITHOGRAPHY, Jap. Appl. Phys., 29p-S-7, 1979; M. Suzuki et al., "PROXIMITY EFFECT CORRECTING METHOD IN ELECTRON-BEAM EXPOSURE", Jap. Appl. Phys., 4a-N-8, 1980; M. Suzuki, et al., "SUBMICRON PATTERN PROXIMITY CORRECTING METHOD IN VARIABLY SHAPED ELECTRON BEAM EXPOSURE", Jap. Appl. Phys., 9p-G-16, 1981; S. Okazaki et al., "ELECTRON BEAM DIRECT WRITING TECHNOLOGY FOR LSI WIRING PROCESS", Ins. of Elec. & Comm., No. 572, 1984, pp. 2-335; M. Okumura et al., "FRAMING PROCESS IN ELECTRON BEAM LITHOGRAPHY", Jan. Appl. Phys., 20a-F-4, 1987; M. Okumura et al., "FRAMING PROCESS IN ELECTRON BEAM LITHOGRAPHY", Jan. Appl. Phys., 20a-F-5, 1987; Japanese Laid-Open Patent Application No. 61-12068 filed on Aug. 8, 1980 corresponding to U.S. Ser. No. 623262; Japanese Laid-Open Patent Application No. 57-45261 filed on May 15, 1982; Japanese Laid-Open Patent Application No. 59-167018 filed on Sep. 20, 1984; or U.S. Pat. No. 4,717,644). The proposed framing processes use shape (figure or pattern) partitioning, which is incorporated with dimension correction and/or dose correction. For example, a pattern to be written is divided into an outer frame and an inner frame. The outer frame is subjected to proximity effect correction, while the inner frame is provided with no correction.